The present invention relates in general to speech and sound synthesizing circuits and more particularly concerns techniques for combining high-efficiency LPC speech synthesizing chips with the low-cost memory of ADPCM audio synthesizing chips.
One example of LPC (linear predictive coding) speech synthesizing chips is the Texas Instruments TSP50CXX family of LPC chips. These chips are highly efficient in their use of stored speech data because their speech synthesizer models a tube of resonant cavities corresponding to the human vocal cords, mouth, etc. Thus, these chips can synthesize speech at a low data rate. TSP50CXX chips are described in the Texas Instruments Design Manual for the TSP50C0X/1X Family Speech Synthesizer and also in U.S. Pat. Nos. 4,234,761, 4,449,233, 4,335,275, and 4,970,659.
An example of ADPCM (adaptive pulse code modulation) audio synthesizing chips is the Sunplus SPC40A, SPC256A, and SPC512A family of chips. These chips produce speech and other sounds at a high data rate. The chips provide low-cost memory because the chips compete with the LPC chips on a cost-per-second basis, and given that their data usage rate is higher than that of the LPC chips by an order of magnitude, these chips must therefore be designed to achieve a cost per memory element that is lower than that of the LPC chips by an order of magnitude. In addition, these chips do not include complex speech synthesis circuitry.